One of his touch points is the ongoing corporate debate over intellectual property and the ways that it either helps or hurts profitability. In a presentation to the World Economic Forum in Davos, he focused on just that issue. He told that gathering of CEOs to watch for certain strategic trends that would indicate that the underlying philosophical foundations of open source were taking root in new areas beyond software and thus validate the constructs of open source as a generalized business model.

 These trends would involve the emergence of self-organizing groups, the formation of large but decentralized teams, and massive rethinks in how sharing intellectual property will enhance competitive standing. Specifically, he pegged companies with sophisticated customers as the ones to observe, as they attempt to do more to work with those customers. "The challenge for the future," he stated, "is to look upon the customer as open source looks to its community and to leverage the expertise among customers."

Last month, those indicators erupted on the semiconductor scene with the force of an emerging volcano, as IBM, a proponent of running Linux everywhere, took up the challenge of putting 'Power Everywhere.' To this end, IBM's goal is to create a “processor ecosphere,” dubbed Power.org, that, in the words of Dr. Irving Wladawsky-Berger, IBM’s Vice President of Technology and Strategy, “starts in the world of consumer technologies and scales to the most powerful supercomputers ever imagined.”

IBM's strategy to achieve that goal is right out of Dr. Katz's playbook. How do you energize a worldwide community of very sophisticated buyers of processor chips? IBM's answer is to provide free access to a wealth of design details and create a governance body from the community. In other words, IBM is extending many open source constructs to its 64-bit Power Architecture.

The full impact of this move has been overshadowed; however, by the highly anticipated release of powerful SMP servers based on the new POWER5 multi-chip module, which combines 4 CPU and 4 cache chips.

The buzz surrounding the POWER5 CPU started building almost a year ago, when IBM revealed the basic design of the POWER5 CPU at the 2003 HotChips conference. What set the cubicles humming in many IT departments? The answer is the addition of Simultaneous Multithreading (SMT). SMT complements the 8-way superscalar chip multiprocessor (CMP) architecture introduced with the POWER4 CPU via support for multiple simultaneously active threads within the core pipeline of a single-processor. SMT helps to insure that all of the chip's execution units are optimally utilized on each clock cycle.

IBM's SMT is conceptually similar to Intel's Hyper-Threading Technology, which is found in the Xeon processor. To implement SMT, IBM added a thread bit to most address/tag buses and replicated completion logic to replicate to track two threads. Nonetheless, the real story of Power Architecture goes way beyond the bounds of Moore’s Law and the next big SMP server upgrade.

For decades, CPU architecture was primarily driven by technological advances in hardware packaging. Ask Dr. Bernie Meyerson, IBM Fellow and Chief Technologist who heads research and development for IBM’s semiconductor group, about what had been the driving force in semiconductors and he’ll tell you that “It was all about thinking small." Why? 

	Smaller transistors are faster.
	Smaller transistors are cheaper.
	Smaller transistors use less power.
	Smaller transistors can be packed more densely.
	Smaller transistors had remarkably predictive properties.

Moore’s Law that CPU power doubles every 18 months is nothing more than an observation on the ability to continuously shrink chip line geometry using well-known CMOS packaging technology. Unfortunately, Moore’s Law, which has taken the industry through many generations of processors, is now facing a higher authority: the second law of thermodynamics.

Fundamental logic elements within digital microprocessors, such as AND gates, work in only one direction, which makes their operation irreversible. Under the second law of thermodynamics, irreversible processes create entropy, which can be loosely considered as heat. So whenever an AND gate clears one bit of data, it generates heat and that requires power. The more AND gates, the more heat gets generated, and the more electrical power gets consumed.

The past success at shrinking line geometry and stretching the limits of hardware packaging is precisely what is now raising the specter of the second law. As you get down to 90nm lithography, which will be used the next generation of POWER5, you have to begin thinking about the knotty question: What happens when the layers of a transistor approach the size of the atoms from which they are made?

Here we begin to leave behind the remarkably predictive properties that we once had and enter a realm where transistors use the same amount of power doing nothing as when they work. Welcome to a preview of the bizarre world of quantum effects. For Dr. Meyerson, that picture is not pretty. “Your new generations of transistors consume dramatically more power than prior experience would have predicted.” On top of that he states, “The performance gains are slower than past experience would have indicated.” So the chilling reality for semiconductor designers is that shrinking hardware packaging can no longer be counted on as a the primary means to drive processor improvements.

As a result, projecting the trajectory of computing performance into the future gets a lot more complicated. IBM seeks to answer this problem by taking a holistic approach to processor technology. To create a vibrant processor ecosystem for the future, Dr. Meyerson’s watchword is “integration: the creation of systems, not just chips.” To create these systems, IBM believes it will be necessary to view hardware packaging, design organization, and the core instruction set as one.

This notion of systems integration at the chip level can be found in an often-overlooked aspect of the implementation of SMT in POWER5 that differentiates it from HTT in Xeon: SMT on POWER5 is dynamic. Some very standard processing tasks, such as matrix multiplication, are execution-unit limited. For these functions, improved performance depends on superscalar CMP features. An extra thread is of no use when the resource that it needs is not available. Worse yet, the extra overhead of tracking an inactive thread lowers performance.

For IBM, the solution is elegantly simple. The POWER5 CPU can dynamically turn off SMT functions.

Take that construct one-step further and you have the answer to Dr. Meyerson’s conundrum over increasing power consumption while shrinking transistors. When transistors use the same amount of power doing nothing as when they work, future chips will need to have a way to morph dynamically and shut down any inactive circuitry. We now begin to grasp a whole new meaning to the concept of a system on a chip (SoC).

These semiconductor design issues go far beyond the domain of high-performance computer CPUs. Today the semiconductor, typically in the guise of an ASIC, has become nearly as pervasive as the screw in consumer products. What's more, the complexity of these ASICs has been increasing exponentially as the number of logic gates has increased from increased from 200,000 to 500,000 in 1997 to upwards of 25 million gates today.

With escalating market pressures making time-to-market a key concern in every product niche, the  complexity of ASIC development has left companies with sophisticated in-house expertise searching for ways to manage the cost of developing and delivering higher-order semiconductor content that keeps up with ever-shortening product life cycles. Many of these companies see the answer to their problem in a paradigm shift away from developing their own ASICs. Their economic mantra is to be fabless, chipless, and a builder SOCs using acquired intellectual property (IP). That's just the kind of customer community that Dr Katz foresaw as ripe for the fruits of open source thinking.

The view of this emerging SOC-integrator community is that ‘platforms’ containing all the basic system-level hardware and firmware can be pre-configured and pre-verified, making it possible to add on highly application-specific IP with little extra cost or effort. Case in point: At the Game Developers Conference, Shin'ichi Okamoto, chief technical officer for Sony Computer Entertainment, spoke to the rationale for the move to Power Architecture: "Moore's Law is too slow for us. We can't wait 20 years to achieve a 1,000-fold increase in PlayStation performance.” In the public spotlight is Sony's next-generation video-game console, the PlayStation 3, which is intended to provide home customers with a cheap, all-in-one box for the home that can record television shows, surf the Net in 3-D, play music, and run movie-like video games.

Seemingly a universe away, the U.S. Department of Energy is tapping into Power Architecture and SoC technology to build a 65,000-processor machine dubbed Blue Gene/Light. The long-term goal of the DoE is to utilize the CMP superscalar functionality and low power consumption of Power Architecture to build petaflop computers for simulation testing for the nation's nuclear arms stockpile.

Blue Gene/L will dig into tasks underlying the missile simulations including molecular modeling, quantum molecular dynamics, fluid turbulence dynamics, and material modeling. To appreciate the scale of Blue Gene/L, it will take up 5,000 feet of floor space and consume 1.2 megawatts of power per year at a cost of $1.2M. The alternative, according to Mark Seager, an assistant director for advanced technologies at Lawrence Livermore Laboratory, would “take 20,000 square feet of new space and 4 to 8 megawatts of power."

We now have the answer to the question: How do we project the trajectory of computing performance into the future? In a word, that answer is innovation. Unfortunately, innovation is very much a two-edged sword. On one hand, only through simultaneous optimization of circuit designs, cores, and systems architecture will performance be effectively optimized. On the other hand, IP solution providers and integrators need a rock-stable platform lest their efforts be wasted by building foundations as transitory as sand.

So if, in the words of Dr Meyerson, “integration eclipses GHz going forward,” then the Power Architecture ecosystem needs a community model that is based on having as its driver the tremendous power of systems integration, and such a community model is clearly that of open source software. It is a community based on the premise that the world is full of incredibly bright people.

Building on that premise, Dr Meyerson wants IBM to be able to say, “Here is Power Architecture, here is the Power core, here is how you hook up and work with it, and here are the tools you need to do so.” To accomplish that task IBM has launched a Web site from which to download all of the tools and access all of the information necessary to begin working with Power Architecture.

Nonetheless, such openness does not prohibit protection of the core instruction set. Much in the same way that the Linux kernel can't be changed willy-nilly, the Power Architecture's core instruction set establishes how everything communicates and cannot be randomly disrupted without invalidating all the prior intellectual property and destroying the ecosystem. As Dr. Meyerson sees it, “It is very important that we protect the people out there doing this sort of work and the only way is to make sure that we absolutely ensure the integrity of the instruction set to which the people are designing their product.”

To the end of constraining information to protect rather than hide, Dr. Meyerson says, “We are looking at the issue of putting together a governance body that will address exactly those questions.”